As the computing speed and data transfer rates of electronic systems has increased, so has the speed at which memory storage devices are required to operate. At the same time, in order to reduce system power consumption, memory storage devices are expected to operate at faster speeds with lower and lower power consumption rates. Among the common types of memory storage devices that are currently employed in electronic systems are various random access memories (RAMS), such as dynamic RAMs (DRAMs) and static RAMs (SRAMs), as well as read only memories (ROMs), such as electrically erasable programmable ROMs (EEPROMs).
In a typical RAM or ROM, the memory device will include a very large number of memory cells arranged into one or more arrays. Each of the memory cells stores a given data value. Data within the memory cell can be accessed by a read or write operation (in the case of a RAM), or a read or program operation (in the case of a ROM). In most RAMs and ROMs, the memory cells are accessed by the application of a row address, which couples a row of memory cells to bit lines. An applied column address will then provide access to selected of the bit lines. The manner by which the row and column addresses are applied varies according to particular memory device type. For example, in conventional DRAMs the row and column address are multiplexed, with the row address being applied first, followed by a column address. In contrast, other higher speed memory devices, such as SRAMs, receive row and column addresses simultaneously. In addition, more current DRAM architectures rely on "packetized" interfaces, in which row and column addresses are received in the same packet of information.
In most memory devices, when a row of memory cells is coupled to the bit lines, data signals are generated on the bit lines. In order to maintain as compact a memory device size as possible, the memory cells are usually manufactured to be as small as possible, resulting in the data signals from the memory cells being correspondingly small (i.e., a small current signal or small voltage signal). In order to translate such small bit line data signals into usable output data signals, the memory device will usually include a bank of sense amplifiers that "sense" the small logic value on a bit lines, and then amplify them to a more usable logic level. Because bit line data signals must first be sensed before they are output, the speed at which such signals can be amplified by sense amplifiers plays an important role in the overall speed of a semiconductor memory device.
In order to amplify bit line data, the typical sense amplifier bank will charge or discharge each bit line according to the sensed memory cell data value. In order to charge the relatively large capacitive load presented by a bit line, a sense amplifier will have to draw current from a supply voltage. Thus, the amplification operation of sense amplifiers can consume considerable current. Current consumption translates directly into power consumption.
In addition to amplifying bit line cell signals to generate output signals, the sense amplifier bank operation also plays an additional role when the memory device is a DRAM. DRAM memory cells typically store data values by charging or discharging a storage capacitor situated within each memory cell. Because stored charge can leak out over time, the charge within such a capacitor must be refreshed in order to preserve the data value. Thus, when a sense operation charges a bit line, the associated storage capacitor will also be charged, refreshing the data value stored within.
A typical DRAM will include a number of memory cell arrays. In a conventional read and refresh arrangement, each memory cell array will include a corresponding sense amplifier bank. Each sense amplifier bank will be coupled to the bit lines of its corresponding memory cell array, and have as many sense amplifiers as there are memory cells in the rows of the array. This allows memory cell data to be refreshed on a row-by-row basis. In this arrangement, in a read or refresh operation, a row of memory cells will be coupled to the bit lines, and hence to a bank of sense amplifiers. The sense amplifier bank is then activated, resulting in the bit lines being charged or discharged simultaneously according to the data on the bit lines. Other approaches have "graded" the turn on of sense amplifiers within a bank, by initially supplying current to the sense amplifiers at one rate, and then increasing the rate.
Due the large number of sense amplifiers in a sense amplifier bank, the current drawn by a memory device can reach a peak when its sense amplifier banks are activated. The peak current is of concern as it translates directly into the amount of power consumed by the semiconductor memory device, and requires that the power supply circuits of the device, and/or the system in which the device is being used, be capable of supplying this peak current. Large peak currents also create unwanted noise on the memory device power supply buses, thus adversely affecting the operation of a memory device.
It would be desirable to provide some way of reducing the peak current drawn by a memory device without adversely affecting the speed of the memory device.